Methods and Tools for Verification of System-Level Designs
by
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
Language: English
Release Date: May 18, 2011
Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level...